The trick in the odd-count case is to note that the CDC system under consideration doesn't impose any restriction on the number of bits actually getting across from one clock domain to the other. How does one extend this to cases where the base counter loops back after an odd number of counts? Consider the case where we want to count from 0 to 6 and back (total of 7 values for the base counter). number of 1s in them, which makes a loop-back possible). Note that the 0 to 5 sequence above has 6 values, which make it easy to create a 'gray' sequence (since each successive value will change by one bit only, they will have odd-even-odd-even. Readers familiar with Johnson counters (twisted ring counters) can recognize that a 3-bit Johnson counter obeys 'gray-code' rules of changing only a single bit between successive values. In the rest of the piece below, we cover an alternative strategy for sequences with low cardinalities (say, between 0 and 31). This the advisable method for large counters. 2 BIT GRAY CODE COUNTER VERILOG CODE SERIESThe textbook method of taking a base sequence, mirroring it and adding it at the end to create a gray code sequence unfortunately doesn't work with non-2 n counters.Ĭlive Maxfield presents a way to create non-2 n gray sequences by pruning pairs from either the top or middle of the mirroring line in Part 3 of his series on Gray code fundamentals. 'Gray Code' Sequence for non-2 n CountersĬonsider a scenario where the binary counter on the left counts from 0 to 5 and back to 0, i.e, the count sequence is (000, 001, 010, 011, 100, 101, 000, 001. Unfortunately, this is where the textbooks stop, but real-world designs don't. The entries into the FIFO won't happen in sequential order, but that won't matter as long as the reading counter in the second domain is also of similar design and reads data from the FIFO in the same order. In most cases, we can use the Gray code counter to directly index into the FIFO and save the cost of the bin2gry conversion. The gry2bin circuit would do the reverse process. The bin2gry circuit would translate the values to the corresponding gray-code sequence (000, 001, 011, 010, 110, 111, 101, 100). For example, with a 3-bit counter, the 'Binary Counter Domain 1' in the above diagram would follow the sequence (000, 001, 010, 011, 100, 101, 110, 111). Most FIFOs have 2 n entries, which can make use of a (n+1) bit counter to keep track of the read and write pointers. For proper CDC, the binary counter needs to undergo a Gray code conversion (using the bin2gry circuit), pass through the synchronizer and undergo the reverse process (using the gry2bin circuit) to get the original counter value. This value needs to get to the second domain so that it may recognize the availability of information in the FIFO. The binary counter on the left in the first clock domain may be the write pointer of a FIFO being used to share information between the two domains. For today's topic, we need to understand how gray codes are used in CDC. A detailed discussion of synchronizers used for CDC is a topic for another day (though we will give it cursory coverage further down in this post). Due to metastability issues when passing multiple bits of information from one clock domain to another, it is imperative that successive values being passed from one domain to another change at most by one bit. Gray codes are used in digital design for clock domain crossing (CDC). So, that will not be the topic of this post. It is pretty easy to create n-bit gray code sequences. Strict gray codes are sequences that have 2 n members and can be created using recursive functions (by taking advantage of the 'mirror image property') I will not go much into examples, as Wikipedia provides a thorough run-down. 2 BIT GRAY CODE COUNTER VERILOG CODE VERIFICATIONDigital design and verification engineers as well as electrical and computer engineering students are aware of the ' Gray code', a sequence of bits in which two successive values differ by only one bit.
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